I82371MX Datasheet, PDF (92/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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When a REQ#/GNT# pair has been designated as an expansion REQ#/GNT# pair, the requesting device must
encode the channel request information (Figure 4), where CH[0:7] are one clock active high states representing
DMA channel requests 0-7 (Note that channel 4 is reserved and must not be asserted). The MPIIX encodes the
granted channel on the GNT# line (bits[0:2]). For example bits[0:2]=011 grants DMA channel 6 and bits[0:2]=100
grants DMA channel 1.
All PCI DMA expansion agents MUST use the channel passing protocol described above. They must also
operate as follows:
1. If a PCI DMA expansion agent has more than one request active, the agent must resend the request serial
protocol after one of the requests has been granted the bus and it has completed its transfer. The expansion
device should negate REQ# for two clocks and then transmit the serial channel passing protocol again, even
if there are no new requests from the PCI expansion agent to the MPIIX. For example, if a PCI expansion
agent had active requests for DMA Channel 1 and a Channel 5, the agent would pass this information to the
MPIIX through the expansion channel passing protocol. If, after receiving GNT# (assume for CH5) and
having the device finish its transfer (device stops driving request to PCI expansion agent), the agent would
then need to re-transmit the expansion channel passing protocol to let the MPIIX know that DMA Channel 1
is still requesting the bus. This must occur, even if DMA Channel 1 is the only request the expansion device
has pending.
2. If a PCI DMA expansion agent has a request go inactive before MPIIX asserts GNT#, the agent must resend
the expansion channel passing protocol. For example, a PCI expansion agent with DMA Channel 1 and 2
requests pending sends these requests to the MPIIX using the expansion channel passing protocol. If DMA
Channel 1 request to the expansion agent goes inactive before a GNT# is received from the MPIIX, the
expansion agent must negate its REQ# line for one clock and resend the expansion channel passing
information with only DMA Channel 2 active.
Note that the MPIIX does not support this case because a DREQ going inactive before a DACK# is received
is not allowed in the ISA DMA protocol. This requirement is needed to be able to support Plug-n-Play ISA
devices that toggle DREQ# lines to determine if those lines are free in the system.
3. If a PCI expansion agent has sent its serial request information and receives a new DMA request before
receiving a GNT#, the agent must resend the serial request with the new request active. For example, If a
PCI expansion agent has already passed requests for DMA Channel 1 and 2 and receives DREQ 3 active
before a GNT# is received, the agent must negate its REQ# line for one clock and resend the expansion
channel passing information with all three channels active.
4.4.4.2. PCI DMA Expansion Cycles
MPIIX’s support of the Mobile PC/PCI DMA Protocol consists of four types of cyclesMemory to I/O, I/O to
Memory, Verify, and ISA master cycles. ISA masters are supported through the use of a DMA Channel that has
been programmed for cascade mode. Single Transfer Mode is implicitly supported as the case where the DMA
controller negates the DACK#/GNT# signal after one transfer has been completed or the DMA controller toggles
DACK# after every transfer. Single transfer mode does not require the requesting device to negate DREQ# after
a cycle has completed. Therefore, a PCI DMA agent that uses this mode must also sample the GNT# signal and
remove DACK# to the I/O DMA device when GNT# is negated.
The DMA controller generates a two cycle transfer (a load followed by a store) in contrast to the ISA "fly-by"
cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory read or memory write
bus cycle with the address representing the selected memory. Refer to the PCI 2.0 specification for timings for
the memory portion of a Mobile PC/PCI DMA cycle.
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses as illustrated in Table 4.
Note that these cycles must be qualified by an active GNT# signal to the requesting device.
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PRELIMINARY