I82371MX Datasheet, PDF (121/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
Suspend DRAM Refresh
In the Suspend to DRAM mode, MTSC uses the 32 KHz RTC clock to trigger the refresh on the falling and rising
edges. The refresh mode selection is described in the MTSC data sheet. Since the HCLK is stopped, the MTSC
uses a ring oscillator to generate the RAS pulses. MTSC disables the ring oscillator if the suspend refresh mode
is set for DRAMs that support Self-Refresh. The suspend refresh is enabled by writing to the SUS_REF bit in the
SUSRSMC1 Register. When this bit is set the SUS_STAT bit is also set, asserting the SUSTAT# signal. The
MTSC suspend refresh logic shadows the SUS_REF bit. When the SUS_REF bit is set, the MTSC enables the
suspend refresh.
4.8.4.3. Suspend Status (SUSTAT#) Signal and Register
Power management software will set the SUS_STAT bit in the SUSRSMC1 Register at the very last stage of the
suspend transition to activate the hardware suspend sequence and resume logic. The SUS_STAT bit can be
directly set by the handler for Suspend-to-Disk or it can be automatically set when the handler enables suspend-
refresh for Suspend-to-DRAM.
When Suspend-to-DRAM or Suspend-to-Disk is enabled and the SUS_STAT bit is set, the SUSTAT# output
signal is driven by the MPIIX. This signal can be used by system components that transition to low power mode
during suspend. In the Suspend-to-Disk mode, the RTC battery voltage is used as the power source for the logic
that drives the SUSTAT# output.
When a Resume Event triggers a system resume, MPIIX negates SUSTAT#. The inactive edge of SUSTAT#
can be used to apply power to the powered down components. The Resume logic initiates a reset sequence,
with some delay, following the SUSTAT# negation.
Resume Event Logic
The resume logic is triggered to exit suspend by the following events:
• RTC alarm (IRQ8#).
• UART ring indication (COMRI#).
• External SMI (EXTSMI#).
• Suspend Resume button press (SRBTN#).
These signals, as well as other resume logic, are in a “Resume Well” that is powered by the RTC battery or the
DRAM power supply that remains powered during Suspend-to-DRAM. For the SRBTN# to be recognized as a
resume event, the system must be in a suspend mode (the SUS_STAT bit is set).
Some of the resume events (COMRI#, IRQ8#, BATLOW#, and EXTSMI#) can be masked such that the system
will not resume as a result of active - masked event. These masks are set in the SUSRSMC[1,2] Registers.
Battery Low indication (BATLOW#) can be masked such that it does not prevent a resume, when both
BATLOW# and a resume event are active. The MPIIX privides a Resume Reset input (RSMRST#) to reset the
entire system (including Resume logic and the RTC content) when the RTC power can not sustain a valid
suspend mode.
The IRQ8# input has an internal 8 KΩ pull-up resister that must always be enabled to maintain a valid logic level
on this input. When the IRQ8# input is masked as a resume event, the interrupt must be disabled at the RTC to
prevent a DC path across the MPIIX internal pull-up resistor.
PRELIMINARY
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