I82371MX Datasheet, PDF (25/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Configuration
Offset
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DB–DFh
E0h
E1–E3h
E4–EAh
EBh
EC–F2h
F3–FFh
Mnemonic
SYSEVNTE0
SYSEVNTE1
SYSEVNTE2
BSTCLKT
CLKC

STPCLKLT
STPCLKHT
STPBRKE0
STPBRKE1
STPBRKE2

SHDW

BSTCLKEE[6:0]

CLKTHLBRKEE[6:0]

Register
System Event Enable 0
System Event Enable 1
System Event Enable 2
Burst Count Timer
Clock Control
Reserved
STPCLK# Low Timer
STPCLK# High Timer
Stop Break Event Enable 0
Stop Break Event Enable 1
Stop Break Event Enable 2
Reserved
Shadow Register
Reserved
Burst Clock Event Enable
Reserved
Clock Throttle Break Event Enable
Reserved
Register
Access
R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
R/W

see
description

R/W

R/W

Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0020h
0021h
0040h
FEDC
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Table 2. ISA-Compatible Registers
Address
BA98
7654
3210
Type
Name
0000
000x
0000
R/W
0000
000x
0001
R/W
0000
000x
0010
R/W
0000
000x
0011
R/W
0000
000x
0100
R/W
0000
000x
0101
R/W
0000
000x
0110
R/W
0000
000x
0111
R/W
0000
000x
1000
R/W
0000
000x
1001
wo
0000
000x
1010
wo
0000
000x
1011
wo
0000
000x
1100
wo
0000
000x
1101
wo
0000
000x
1110
wo
0000
000x
1111
R/W
0000
001x
xx00
R/W
0000
001x
xx01
R/W
0000
010x
0000
R/W
DMA1 CH0 Base and Current Address
DMA1 CH0 Base and Current Count
DMA1 CH1 Base and Current Address
DMA1 CH1 Base and Current Count
DMA1 CH2 Base and Current Address
DMA1 CH2 Base and Current Count
DMA1 CH3 Base and Current Address
DMA1 CH3 Base and Current Count
DMA1 Status(r) Command(w) register
DMA1 Write Request register
DMA1 Write Single Mask Bit
DMA1 Write Mode register
DMA1 Clear Byte Pointer
DMA1 Master Clear
DMA1 Clear Mask register
DMA1 Read/Write All Mask Register Bits
INT 1 Control register
INT 1 Mask register
Timer Counter 1 – Counter 0 Count
PRELIMINARY
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