I82371MX Datasheet, PDF (56/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
3.2.58. SYSEVNTE0—System EVENT Enable 0 Register
Address Offset:
Default Value:
Attribute:
D0h
00h
Read/Write
This register enables hardware events as system events for power management control.
Bit
Description
7
SYS_EVNT_EN_IRQ_7. 1=Enable IRQ7 as a System Event.
6
SYS_EVNT_EN_IRQ_6. 1=Enable IRQ6 as a System Event.
5
SYS_EVNT_EN_IRQ_5. 1=Enable IRQ5 as a System Event.
4
SYS_EVNT_EN_IRQ_4. 1=Enable IRQ4 as a System Event.
3
SYS_EVNT_EN_IRQ_3. 1=Enable IRQ3 as a System Event.
2
Reserved.
1
SYS_EVNT_EN_IRQ_1. 1=Enable IRQ1 as a System Event.
0
SYS_EVNT_EN_IRQ_0. 1=Enable IRQ0 as a System Event.
E
3.2.59. SYSEVNTE1—System EVENT Enable 1 Register
Address Offset:
Default Value:
Attribute:
D1h
00h
Read/Write
This register enables hardware events as system events for power management control.
Bit
Description
7
SYS_EVNT_EN_IRQ_15. 1=Enable IRQ15 as a System Event.
6
SYS_EVNT_EN_IRQ_14. 1=Enable IRQ14 as a System Event.
5
Reserved.
4
SYS_EVNT_EN_IRQ_12. 1=Enable IRQ12 as a System Event.
3
SYS_EVNT_EN_IRQ_11. 1=Enable IRQ11 as a System Event.
2
SYS_EVNT_EN_IRQ_10. 1=Enable IRQ10 as a System Event.
1
SYS_EVNT_EN_IRQ_9. 1=Enable IRQ9 as a System Event.
0
SYS_EVNT_EN_IRQ_8. 1=Enable IRQ8# as a System Event.
56
PRELIMINARY