I82371MX Datasheet, PDF (3/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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CONTENTS
82371MX (MPIIX)
1.0. ARCHITECTURE OVERVIEW................................................................................................................9
2.0 SIGNAL DESCRIPTION..........................................................................................................................11
2.1. PCI Interface Signals.............................................................................................................................. 11
2.2. IDE Interface Signals.............................................................................................................................. 13
2.3. Extended I/O Bus Signals ...................................................................................................................... 14
2.4. Motherboard I/O Device Interface Signals ............................................................................................ 15
2.5. DMA Signals ........................................................................................................................................... 17
2.6. Interrupt Controller Signals .................................................................................................................... 17
2.7. System Power Management ( SMM) Signals ........................................................................................ 19
2.8. System Clock And Reset Signals ..........................................................................................................20
2.9. Test Signals ............................................................................................................................................ 21
3.0. REGISTER DESCRIPTION....................................................................................................................22
3.1. Register Access ......................................................................................................................................22
3.2. PCI Configuration Registers .................................................................................................................. 27
3.2.1. VID—VENDOR IDENTIFICATION REGISTER ............................................................................ 27
3.2.2. DID—DEVICE IDENTIFICATION REGISTER .............................................................................. 27
3.2.3. COM—COMMAND REGISTER .....................................................................................................28
3.2.4. DS—DEVICE STATUS REGISTER .............................................................................................. 28
3.2.5. RID—REVISION IDENTIFICATION REGISTER ..........................................................................29
3.2.6. CLASSC—CLASS CODE REGISTER .......................................................................................... 29
3.2.7. HEDT—HEADER TYPE REGISTER ............................................................................................ 30
3.2.8. SPPE—SERIAL & PARALLEL PORT ENABLE REGISTER ...................................................... 30
3.2.9. ECRT— EXTENDED I/O CONTROLLER RECOVERY TIMER REGISTER ............................. 31
3.2.10. BIOSE — BIOS ENABLE REGISTER ......................................................................................... 31
3.2.11. FDCE—FDC ENABLE REGISTER ............................................................................................. 32
3.2.12. PIRQRC [A,B]—PIRQX ROUTE CONTROL REGISTERS ........................................................ 33
3.2.13. MSTAT—MISCELLANEOUS STATUS REGISTER ..................................................................33
3.2.14. IDETIM—IDE TIMING REGISTER .............................................................................................. 34
3.2.15. MIRQRC—MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTER .......................... 35
3.2.16. MDMARC[2:0]MOTHERBOARD DEVICE DMA ROUTE CONTROL REGISTERS ............ 36
3.2.17. AUDIOE—AUDIO ENABLE REGISTER .................................................................................... 37
3.2.18. DMADS—DMA CH[7:5] DATA SIZE REGISTER .......................................................................37
3.2.19. PCIDMAE—PCI DMA ENABLE REGISTER .............................................................................. 37
3.2.20. PCIDMA[A,B]PCI DMA AND PCI DMA EXPANSION REGISTER .......................................38
3.2.21. PMAC[1:0]—PROGRAMMABLE MEMORY ADDRESS CONTROL REGISTERS ................. 39
3.2.22. PMAM[1:0]—PROGRAMMABLE MEMORY ADDRESS MASK REGISTERS ......................... 40
3.2.23. PARE—PROGRAMMABLE ADDRESS RANGE ENABLE REGISTER ...................................40
3.2.24. PCSC—PROGRAMMABLE CHIP SELECT CONTROL REGISTER .......................................41
PRELIMINARY
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