I82371MX Datasheet, PDF (17/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
2.5. DMA Signals
Signal Name
Type
MDRQ[2:0]/
EXTEVNT#
I
5V
pd50K
Ω
MDAK[2:0]#/
PAD#
O
5V
4mA
PCIRST#
High
DREQ2
DACK2#
TC
I
5V
pu50K
Ω
TTL
O
5V
TTL
4mA
High
O
5V
TTL
4mA
Tri-state
82371MX (MPIIX)
Description
MOTHERBOARD DEVICE DMA REQUEST: These
signals can be connected internally to any of
DREQ[3:0,7:5]. Each pair of request/acknowledge
signals is controlled by a separate register.
MOTHERBOARD DEVICE DMA ACKNOWLEDGE:
These signals can be connected internally to any of
DACK[3:0,7:5]. Each pair of request/acknowledge
signals is controlled by a separate register. MDAK1 or
MDAK2 or both can be enabled to re-load the Local
Standby Timer for the audio device.
DMA REQUEST 2: DREQ2 is used by the floppy disk
controller to request DMA service from the MPIIX's DMA
controller. All inactive to active edges are assumed to be
asynchronous. The request must remain active until the
appropriate DACK2# signal is asserted.
DMA ACKNOWLEDGE 2: DACK2# indicates that a
request for DMA service has been granted by the
MPIIX. This line should be used to decode the DMA
slave device with the IOR# or IOW# line to indicate
selection.
TERMINAL COUNT: The MPIIX asserts TC to DMA
slaves as a terminal count indicator. MPIIX asserts TC
after a new address has been output, if the byte count
expires with that transfer. When all the DMA channels
are not in use, TC is negated (low).
2.6. Interrupt Controller Signals
Signal Name
Type
PCIRST#
IRQ[15,14,
11:9,7:3,1]
I
5V
pu8KΩ
TTL
Description
INTERRUPT REQUEST: The IRQ signals provide both
system board components and docking station Extended I/O
Bus I/O devices with a mechanism for asynchronously
interrupting the CPU. The assertion mode of these inputs
depends on the programming of the two ELCR Registers.
IRQ1 (as well as IRQ[8#,2,0] and the internal IRQ13) are not
programmable through the ELCR Registers. These IRQs are
always active high edge triggered. An internal flip-flop latches
a low-to-high transition on IRQ1. The MPIIX continues to
generate an internal IRQ1 to the 8259 core until a PCIRST#
or an I/O read access to port 60h.
An active IRQ input must remain asserted until after the
interrupt is acknowledged. If the IRQ is negated before this
time, a DEFAULT IRQ7 occurs when the CPU acknowledges
the interrupt.
PRELIMINARY
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