S912XEG384J3VA Datasheet, PDF (93/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Port Pin Name
T
PT[7]
PT[5]
PT[4:0]
S
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Pin Function
& Priority⁽¹⁾
IOC[7]
GPIO
IOC[5]
VREG_API
GPIO
IOC[4:0]
GPIO
SS0
GPIO
SCK0
GPIO
MOSI0
GPIO
MISO0
GPIO
TXD1
GPIO
RXD1
GPIO
TXD0
GPIO
RXD0
GPIO
I/O
Description
Pin Function
after Reset
I/O Enhanced Capture Timer Channels 7 input/output
I/O General-purpose I/O
GPIO
I/O Enhanced Capture Timer Channel 5 input/output
O VREG Autonomous Periodical Interrupt output
I/O General-purpose I/O
I/O Enhanced Capture Timer Channels 4 - 0 input/output
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 slave select output in master mode,
input in slave mode or master mode.
I/O General-purpose I/O
GPIO
I/O Serial Peripheral Interface 0 serial clock pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master out/slave in pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master in/slave out pin
I/O General-purpose I/O
O Serial Communication Interface 1 transmit pin
I/O General-purpose I/O
I Serial Communication Interface 1 receive pin
I/O General-purpose I/O
O Serial Communication Interface 0 transmit pin
I/O General-purpose I/O
I Serial Communication Interface 0 receive pin
I/O General-purpose I/O
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
93