S912XEG384J3VA Datasheet, PDF (122/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.22 Port T Input Register (PTIT)
Address 0x0241
7
R PTIT7
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
1. Read: Anytime.
Figure 2-20. Port T Input Register (PTIT)
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIT1
0
PTIT0
u
u
Field
7-0
PTIT
Table 2-21. PTIT Register Field Descriptions
Description
Port T input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.23 Port T Data Direction Register (DDRT)
Address 0x0242
R
W
Reset
7
DDRT7
0
1. Read: Anytime.
Write: Anytime.
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 2-21. Port T Data Direction Register (DDRT)
Access: User read/write⁽¹⁾
1
0
DDRT1
DDRT0
0
0
Table 2-22. DDRT Register Field Descriptions
Field
7-0
DDRT
Description
Port T data direction—
This register controls the data direction of pins 7 through 0.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
MC9S12XE-Family Reference Manual Rev. 1.25
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