S912XEG384J3VA Datasheet, PDF (1031/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
Table 27-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 27.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
27.3.2.5 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
R
W
Reset
7
CCIE
0
6
5
4
3
2
0
0
0
0
IGNSF
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-9. Flash Configuration Register (FCNFG)
1
FDFD
0
0
FSFD
0
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 27-15. FCNFG Field Descriptions
Field
7
CCIE
4
IGNSF
Description
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 27.3.2.7)
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 27.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
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