S912XEG384J3VA Datasheet, PDF (848/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
Table 24-15. FCNFG Field Descriptions (continued)
Field
1
FDFD
0
FSFD
Description
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 24.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 24.3.2.6)
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 24.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 24.3.2.6)
24.3.2.6 Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
7
6
5
4
3
2
1
R
0
ERSERIE PGMERIE
EPVIOLIE ERSVIE1 ERSVIE0
DFDIE
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-10. Flash Error Configuration Register (FERCNFG)
0
SFDIE
0
All assigned bits in the FERCNFG register are readable and writable.
Table 24-16. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see Section 24.3.2.8)
6
PGMERIE
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see Section 24.3.2.8)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see Section 24.3.2.8)
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