S912XEG384J3VA Datasheet, PDF (228/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 4 Memory Protection Unit (S12XMPUV1)
access is allowed or represents an access violation. If an access violation caused by the S12X CPU is
detected, the MPU module raises an access violation interrupt. If the MPU module detects an access
violation caused by a bus master other than the S12X CPU, it flags an access error condition to the
respective master. In addition to the restrictions defined for memory ranges in the MPU descriptors,
accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access
violations.
Figure 4-1 shows a block diagram of the MPU module.
Data Access
Op-code Fetch
MPU Monitoring
Access Validation
MPU
CPU
Data Access
Op-code Fetch
MPU Monitoring
Access Validation
XGATE
Data Access
“Master3”
MPU Monitoring
Access Validation
MMC
Status
Registers
Figure 4-1. Block Diagram
Access Violation
Interrupt
4.1.3 Features
• Protects memory from undesired accesses coming from up to 3 bus masters¹
• Eight memory protection descriptors
— each descriptor can cover the full global memory map (8 MBytes)
— each descriptor has a granularity of 8 Bytes
1. Master 3 can be implemented or left out depending the chip configuration. Please refer to the Device Reference Manual for
information about the availability and function of Master 3.
MC9S12XE-Family Reference Manual Rev. 1.25
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