S912XEG384J3VA Datasheet, PDF (264/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 6 Interrupt (S12XINTV2)
6.1.4 Block Diagram
Figure 6-1 shows a block diagram of the XINT module.
Peripheral
Interrupt Requests
Non I Bit Maskable
Channels
IRQ Channel
Wake Up
CPU
Vector
Address
RQST
One Set Per Channel
(Up to 108 Channels)
XGATE
Requests
PRIOLVL2
PRIOLVL1
PRIOLVL0
Interrupt
Requests
INT_XGPRIO
IVBR
New
IPL
Current
IPL
Priority
Decoder
Wake up
XGATE
Vector
ID
XGATE
Interrupts
To XGATE Module
RQST
XGATE Request Route,
PRIOLVLn Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR
= Interrupt Vector Base
IPL
= Interrupt Processing Level
Figure 6-1. XINT Block Diagram
6.2 External Signal Description
The XINT module has no external signals.
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor