S912XEG384J3VA Datasheet, PDF (34/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 1 Device Overview MC9S12XE-Family
Table 1-1. Device Register Memory Map (continued)
Address
0x0200–0x023F
0x0240–0x027F
0x0280–0x02BF
0x02C0–0x02EF
0x02F0–0x02F7
0x02F8–0x02FF
0x0300–0x0327
0x0328–0x032F
0x0330–0x0337
0x0338–0x033F
0x0340–0x0367
0x0368–0x037F
0x0380–0x03BF
0x03C0–0x03CF
0x03D0–0x03FF
0x0400–0x07FF
Module
Size
(Bytes)
CAN3
PIM (port integration module)
CAN4
ATD0 (analog-to-digital converter 12 bit 16-channel)
Voltage regulator
Reserved
PWM (pulse-width modulator 8 channels)
Reserved
SCI6 (serial communications interface)
SCI7 (serial communications interface)
PIT (periodic interrupt timer)
PIM (port integration module)
XGATE
Reserved
TIM (timer module)
Reserved
64
64
64
48
8
8
40
8
8
8
40
24
64
16
48
1024
NOTE
Reserved register space shown in Table 1-1 is not allocated to any module.
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
1.1.5 Address Mapping
Figure 1-2 shows S12XE CPU & BDM local address translation to the global memory map. It indicates
also the location of the internal resources in the memory map.
EEEPROM size is presented like a fixed 256 KByte in the memory map.
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor