S912XEG384J3VA Datasheet, PDF (553/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
All bits reset to zero.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents
are respectively the high and low byte of the PACB.
When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
14.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Module Base + 0x0026
R
W
Reset
7
MCZI
0
6
MODMC
0
5
RDMCL
0
4
0
ICLAT
0
3
0
FLMC
0
2
MCEN
0
1
MCPR1
0
Figure 14-42. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
0
MCPR0
0
Table 14-23. MCCTL Field Descriptions
Field
Description
7
MCZI
6
MODMC
5
RDMCL
Modulus Counter Underflow Interrupt Enable
0 Modulus counter interrupt is disabled.
1 Modulus counter interrupt is enabled.
Modulus Mode Enable
0 The modulus counter counts down from the value written to it and will stop at 0x0000.
1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest
value written to the modulus count register.
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
the modulus counter to 0xFFFF.
Read Modulus Down-Counter Load
0 Reads of the modulus count register (MCCNT) will return the present value of the count register.
1 Reads of the modulus count register (MCCNT) will return the contents of the load register.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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