S912XEG384J3VA Datasheet, PDF (126/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-26. PTS Register Field Descriptions (continued)
Field
1
PTS
0
PTS
Description
Port S general purpose input/output data—Data Register
Port S pin 3 is associated with the TXD signal of the SCI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S bits 2 is associated with the RXD signal of the SCI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.30 Port S Input Register (PTIS)
Address 0x0249
7
R PTIS7
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
1. Read: Anytime.
Figure 2-28. Port S Input Register (PTIS)
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIS1
0
PTIS0
u
u
Field
7-0
PTIS
Table 2-27. PTIS Register Field Descriptions
Description
Port S input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.31 Port S Data Direction Register (DDRS)
Address 0x024A
R
W
Reset
7
DDRS7
0
1. Read: Anytime.
Write: Anytime.
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 2-29. Port S Data Direction Register (DDRS)
Access: User read/write⁽¹⁾
1
0
DDRS1
DDRS0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
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