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S912XEG384J3VA Datasheet, PDF (631/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family | |||
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Chapter 16 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 16-26. Message Buffer Organization
Offset
Address
Register
0x00X0 IDR0 â Identiï¬er Register 0
0x00X1 IDR1 â Identiï¬er Register 1
0x00X2 IDR2 â Identiï¬er Register 2
0x00X3 IDR3 â Identiï¬er Register 3
0x00X4 DSR0 â Data Segment Register 0
0x00X5 DSR1 â Data Segment Register 1
0x00X6 DSR2 â Data Segment Register 2
0x00X7 DSR3 â Data Segment Register 3
0x00X8 DSR4 â Data Segment Register 4
0x00X9 DSR5 â Data Segment Register 5
0x00XA DSR6 â Data Segment Register 6
0x00XB DSR7 â Data Segment Register 7
0x00XC
0x00XD
DLR â Data Length Register
TBPR â Transmit Buffer Priority Register(1)
0x00XE TSRH â Time Stamp Register (High Byte)
0x00XF TSRL â Time Stamp Register (Low Byte)
1. Not applicable for receive buffers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Figure 16-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identiï¬ers. The mapping of standard identiï¬ers into the IDR registers is shown in Figure 16-25.
All bits of the receive and transmit buffers are âxâ out of reset because of RAM-based implementation1.
All reserved or unused bits of the receive and transmit buffers always read âxâ.
1. Exception: The transmit buffer priority registers are 0 out of reset.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
631
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