S912XEG384J3VA Datasheet, PDF (170/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.94 Port L Input Register (PTIL)
Address 0x0371
7
R PTIL7
6
PTIL6
5
PTIL5
4
PTIL4
3
PTIL3
2
PTIL2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
1. Read: Anytime.
Figure 2-92. Port L Input Register (PTIL)
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIL1
0
PTIL0
u
u
Field
7-0
PTIL
Table 2-89. PTIL Register Field Descriptions
Description
Port L input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.95 Port L Data Direction Register (DDRL)
Address 0x0372
R
W
Reset
7
DDRL7
0
1. Read: Anytime.
Write: Anytime.
6
DDRL6
5
DDRL5
4
DDRL4
3
DDRL3
2
DDRL2
0
0
0
0
0
Figure 2-93. Port L Data Direction Register (DDRL)
Access: User read/write⁽¹⁾
1
0
DDRL1
DDRL0
0
0
Table 2-90. DDRL Register Field Descriptions
Field
7-0
DDRL
Description
Port L data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port L pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XE-Family Reference Manual Rev. 1.25
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