S912XEG384J3VA Datasheet, PDF (193/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

3.3.2 Register Descriptions
Chapter 3 Memory Mapping Control (S12XMMCV4)
3.3.2.1 MMC Control Register (MMCCTL0)
Address: 0x000A PRR
7
R
CS3E1
W
6
CS3E0
5
CS2E1
4
CS2E0
Reset
0
0
0
0
1. ROMON is bit[0] of the register MMCTL1 (see Figure 3-10)
= Unimplemented or Reserved
3
CS1E1
0
2
CS1E0
0
Figure 3-3. MMC Control Register (MMCCTL0)
1
CS0E1
0
0
CS0E0
ROMON¹
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 3-5. Chip Selects Function Activity
Register Bit
Chip Modes
NS
SS
NX
ES
CS0E[1:0], CS1E[1:0],
Disabled⁽¹⁾
CS2E[1:0], CS3E[1:0]
1. Disabled: feature always inactive.
Disabled
Enabled⁽²⁾
2. Enabled: activity is controlled by the appropriate register bit value.
Disabled
EX
Enabled
ST
Disabled
The MMCCTL0 register is used to control external bus functions, like:
• Availability of chip selects. (See Table 3-5 and Table 3-6)
• Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
193