S912XEG384J3VA Datasheet, PDF (249/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-9. Summary of Functions (continued)
Properties
(if Enabled)
Single-Chip Modes
Normal
Special
Single-Chip Single-Chip
Normal
Expanded
Expanded Modes
Emulation
Single-Chip
Emulation
Expanded
Special
Test
Flash area
—
—
—
1 cycle
1 cycle
1 cycle
address access⁽⁴⁾
Signal Properties
Bus signals
—
—
ADDR[22:1] ADDR[22:20]/ ADDR[22:20]/ ADDR[22:0]
DATA[15:0]
ACC[2:0]
ACC[2:0]
DATA[15:0]
ADDR[19:16]/ ADDR[19:16]/
IQSTAT[3:0] IQSTAT[3:0]
ADDR[15:0]/ ADDR[15:0]/
IVD[15:0]
IVD[15:0]
DATA[15:0]
DATA[15:0]
Data select signals
—
(if 16-bit data bus)
—
UDS
ADDR0
ADDR0
ADDR0
LDS
LSTRB
LSTRB
LSTRB
Data direction signals
—
—
RE
RW
RW
RW
WE
Chip Selects
—
CS0
CS0
—
CS1
CS2
—
CS1
CS2
—
CS3
CS3
External wait
—
feature
—
EWAIT
—
EWAIT
—
Reduced input
—
threshold enabled on
1. Incl. S12X_EBI registers
—
Refer to
DATA[15:0]
DATA[15:0]
Refer to
Table 5-4
EWAIT
EWAIT
Table 5-4
2. Refer to S12X_MMC section.
3. If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4. Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
5.4.2 Internal Visibility
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 5-12 to
Table 5-14), internal writes on ADDRx and DATAx (see Table 5-15 to Table 5-17). RW and LSTRB
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
249