S912XEG384J3VA Datasheet, PDF (376/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
XGVBR
+$0000
unused
+$0024 _{Channel $09 Initial Program Counter}
Channel $09 Initial Data Pointer
+$0028 _{Channel $0A Initial Program Counter}
Channel $0A Initial Data Pointer
+$002C _{Channel $0B Initial Program Counter}
Channel $0B Initial Data Pointer
+$0030 _{Channel $0C Initial Program Counter}
Channel $0C Initial Data Pointer
Code
Data
Code
+$01E0 _{Channel $78 Initial Program Counter}
Channel $78 Initial Data Pointer
Figure 10-23. XGATE Vector Block
Data
10.4.4 Semaphores
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism
to protect system resources that are shared between two concurrent threads of program execution; one
thread running on the S12X_CPU and one running on the XGATE RISC core.
Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked
by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore
register (XGSEM, see Section 10.3.1.10, “XGATE Semaphore Register (XGSEM)”). The RISC core does
this through its SSEM and CSEM instructions.
IFigure 10-24 illustrates the valid state transitions.
MC9S12XE-Family Reference Manual Rev. 1.25
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