S912XEG384J3VA Datasheet, PDF (665/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
Table 17-3. PITFLT Field Descriptions
Field
Description
7:0
PFLT[7:0]
PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
17.3.0.3 PIT Channel Enable Register (PITCE)
Module Base + 0x0002
R
W
Reset
7
PCE7
0
6
PCE6
5
PCE5
4
PCE4
3
PCE3
2
PCE2
0
0
0
0
0
Figure 17-5. PIT Channel Enable Register (PITCE)
1
PCE1
0
0
PCE0
0
Read: Anytime
Write: Anytime
Table 17-4. PITCE Field Descriptions
Field
Description
7:0
PCE[7:0]
PIT Enable Bits for Timer Channel 7:0 — These bits enable the PIT channels 7-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
17.3.0.4 PIT Multiplex Register (PITMUX)
Module Base + 0x0003
R
W
Reset
7
PMUX7
0
6
PMUX6
5
PMUX5
4
PMUX4
3
PMUX3
2
PMUX2
0
0
0
0
0
Figure 17-6. PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime
1
PMUX1
0
0
PMUX0
0
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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