S912XEG384J3VA Datasheet, PDF (187/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 3
Memory Mapping Control (S12XMMCV4)
Table 3-1. Revision History
Revision
Number
V04.04
Revision Date
26 Oct 2005
Sections
Affected
Description of Changes
- Reorganization of MEMCTL0 register bits.
V04.05
26 Jul 2006
3.4.2.4/3-212 - Updated XGATE Memory Map
V04.06
15 Nov 2006
- Adding AUTOSAR Compliance concerning illegal CPU accesses
3.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in Figure 3-1.
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses, including internal memories and peripherals, are controlled in this module.
The local address space for each master is translated to a global memory space.
MC9S12XE-Family Reference Manual Rev. 1.25
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