S912XEG384J3VA Datasheet, PDF (61/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 1 Device Overview MC9S12XE-Family
Table 1-10. Signal Properties Summary (Sheet 4 of 4)
Pin
Name
Function 1
Pin
Name
Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
Power
Supply
PP4
KWP4
PWM4
MISO2 TIMIOC4 V_DDX
PP3
KWP3
PWM3
SS1
TIMIOC3 V_DDX
PP2
KWP2
PWM2
SCK1 TIMIOC2 V_DDX
PP1
KWP1
PWM1
MOSI1 TIMIOC1 V_DDX
PP0
KWP0
PWM0
MISO1 TIMIOC0 V_DDX
PR[7:0] TIMIOC
—
—
[7:0]
PS7
SS0
—
—
PS6
SCK0
—
—
PS5
MOSI0
—
—
PS4
MISO0
—
—
PS3
TXD1
—
—
PS2
RXD1
—
—
PS1
TXD0
—
—
PS0
RXD0
—
—
PT[7:6] IOC[7:6]
—
—
PT[5]
IOC[5] VREGAPI
—
PT[4:0] IOC[4:0]
—
—
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
—
V_DDX
Internal Pull
Resistor
CTRL
Reset
State
Description
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
4 of PWM/TIM, MISO2 of
SPI2
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
3 of PWM/TIM, SS of SPI1
Disabled Port P I/O, interrupt, channel
2 of PWM/TIM, SCK of SPI1
Disabled Port P I/O, interrupt, channel
1 of PWM/TIM, MOSI of
SPI1
Disabled Port P I/O, interrupt, channel
0 of PWM/TIM, MISO2 of
SPI1
PERR/
PPSR
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
Disabled Port RI/O, TIM channels
Up Port S I/O, SS of SPI0
Up Port S I/O, SCK of SPI0
Up Port S I/O, MOSI of SPI0
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
Up Port S I/O, MISO of SPI0
Up Port S I/O, TXD of SCI1
Up Port S I/O, RXD of SCI1
Up Port S I/O, TXD of SCI0
PERS/
PPSS
Up Port S I/O, RXD of SCI0
PERT/
PPST
PERT/
PPST
PERT/
PPST
Disabled Port T I/O, ECT channels
Disabled Port T I/O, ECT channels
Disabled Port T I/O, ECT channels
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
61