S912XEG384J3VA Datasheet, PDF (1113/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
FCMD
0x08
0x0B
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x20
Table 28-32. D-Flash Commands
Command
Erase All Blocks
Unsecure Flash
Set User Margin
Level
Set Field Margin
Level
Full Partition D-
Flash
Erase Verify D-
Flash Section
Program D-Flash
Erase D-Flash
Sector
Enable EEPROM
Emulation
Disable EEPROM
Emulation
EEPROM
Emulation Query
Partition D-Flash
Function on D-Flash Memory
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
Specifies a user margin read level for the D-Flash block.
Specifies a field margin read level for the D-Flash block (special modes only).
Erase the D-Flash block and partition an area of the D-Flash block for user access.
Verify that a given number of words starting at the address provided are erased.
Program up to four words in the D-Flash block.
Erase all bytes in a sector of the D-Flash block.
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
Returns EEE partition and status variables.
Partition an area of the D-Flash block for user access.
28.4.2 Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 28.3.2.7).
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