S912XEG384J3VA Datasheet, PDF (366/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
63
R
XGIF_3F
W
62
XGIF_3E
61
XGIF_3D
60
XGIF_3C
59
XGIF_3B
58
XGIF_3A
57
XGIF_39
56
XGIF_38
55
XGF _37
54
XGIF_36
53
XGIF_35
52
XGIF_34
51
XGIF_33
50
XGIF_32
49
XGIF_31
48
XGIF_30
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47
R
XGIF_2F
W
46
XGIF_2E
45
XGIF_2D
44
XGIF_2C
43
XGIF_2B
42
XGIF_2A
41
XGIF_29
40
XGIF_28
39
XGF _27
38
XGIF_26
37
XGIF_25
36
XGIF_24
35
XGIF_23
34
XGIF_22
33
XGIF_21
32
XGIF_20
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
R
XGIF_1F
W
30
XGIF_1E
29
XGIF_1D
28
XGIF_1C
27
XGIF_1B
26
XGIF_1A
25
XGIF_19
24
XGIF_18
23
XGF _17
22
XGIF_16
21
XGIF_15
20
XGIF_14
19
XGIF_13
18
XGIF_12
17
XGIF_11
16
XGIF_10
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
XGIF_0F XGIF_0E XGIF_0D
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-10. XGATE Channel Interrupt Flag Vector (XGIF) (continued)
Read: Anytime
Write: Anytime
Table 10-10. XGIV Field Descriptions
Field
Description
127–9
XGIF[78:9]
Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC
core (see SIF instruction on page 10-449). Each flag can be cleared by writing a "1" to its bit location.
Unimplemented interrupt flags will always read "0". Section “Interrupts” of the device overview for a list of
implemented Interrupts.
Read:
0 Channel interrupt is not pending
1 Channel interrupt is pending if XGIE is set
Write:
0 No effect
1 Clears the interrupt flag
MC9S12XE-Family Reference Manual Rev. 1.25
366
Freescale Semiconductor