S912XEG384J3VA Datasheet, PDF (172/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.98 Port L Polarity Select Register (PPSL)
Address 0x0375
R
W
Reset
7
PPSL7
0
1. Read: Anytime.
Write: Anytime.
6
PPSL6
5
PPSL5
4
PPSL4
3
PPSL3
2
PPSL2
0
0
0
0
0
Figure 2-96. Port L Polarity Select Register (PPSL)
Access: User read/write⁽¹⁾
1
0
PPSL1
PPSL0
0
0
Table 2-93. PPSL Register Field Descriptions
Field
7-0
PPSL
Description
Port L pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
2.3.99 Port L Wired-Or Mode Register (WOML)
Address 0x0376
R
W
Reset
7
WOML7
0
1. Read: Anytime.
Write: Anytime.
6
WOML6
5
WOML5
4
WOML4
3
WOML3
2
WOML2
0
0
0
0
0
Figure 2-97. Port L Wired-Or Mode Register (WOML)
Access: User read/write⁽¹⁾
1
0
WOML1
WOML0
0
0
Table 2-94. WOML Register Field Descriptions
Field
Description
7-0
WOML
Port L wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or independent of the function used on the pins. If enabled the
output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of
several serial modules. These bits have no influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
MC9S12XE-Family Reference Manual Rev. 1.25
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