S912XEG384J3VA Datasheet, PDF (161/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR0AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
2.3.80 Port AD1 Data Direction Register 1 (DDR1AD1)
Address 0x027B
Access: User read/write⁽¹⁾
7
R
DDR1AD17
W
6
DDR1AD16
5
DDR1AD15
4
DDR1AD14
3
DDR1AD13
2
DDR1AD12
1
DDR1AD11
0
DDR1AD10
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-78. Port AD1 Data Direction Register 1 (DDR1AD1)
Table 2-76. DDR1AD1 Register Field Descriptions
Field
Description
7-0 Port AD1 data direction—
DDR1AD1 This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR1AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
161