S912XEG384J3VA Datasheet, PDF (317/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
Table 8-21. State Control Register Access Encoding
COMRV
00
01
10
11
Visible State Control Register
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
8.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-22. DBGSCR1 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State1, based upon the match event.
SC[3:0]
0000
0001
0010
Table 8-23. State1 Sequencer Next State Selection
Description
Any match triggers to state2
Any match triggers to state3
Any match triggers to Final State
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
317