S912XEG384J3VA Datasheet, PDF (579/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 15
Inter-Integrated Circuit (IICV3) Block Description
Table 15-1. Revision History
Revision
Number
V01.03
V01.04
V01.05
Revision Date
28 Jul 2006
17 Nov 2006
14 Aug 2007
Sections
Affected
Description of Changes
15.7.1.7/15-601 - Update flow-chart of interrupt routine for 10-bit address
15.3.1.2/15-582 - Revise Table1-5
15.3.1.1/15-581 - Backward compatible for IBAD bit name
15.1 Introduction
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of
connections between devices, and eliminates the need for an address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
15.1.1 Features
The IIC module has the following key features:
• Compatible with I2C bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
579