S912XEG384J3VA Datasheet, PDF (160/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.78 Port AD1 Data Register 1 (PT1AD1)
Address 0x0279
7
R
PT1AD17
W
Altern.
Function
AN7
Reset
0
1. Read: Anytime.
Write: Anytime.
6
PT1AD16
5
PT1AD15
4
PT1AD14
3
PT1AD13
2
PT1AD12
AN6
AN5
AN4
AN3
AN2
0
0
0
0
0
Figure 2-76. Port AD1 Data Register 1 (PT1AD1)
Access: User read/write⁽¹⁾
1
0
PT1AD11 PT1AD10
AN1
AN0
0
0
Table 2-74. PT1AD1 Register Field Descriptions
Field
Description
7-0
PT1AD1
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.79 Port AD1 Data Direction Register 0 (DDR0AD1)
Address 0x027A
Access: User read/write⁽¹⁾
7
R
DDR0AD17
W
6
DDR0AD16
5
DDR0AD15
4
DDR0AD14
3
DDR0AD13
2
DDR0AD12
1
DDR0AD11
0
DDR0AD10
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)
Table 2-75. DDR0AD1 Register Field Descriptions
Field
Description
7-0 Port AD1 data direction—
DDR0AD1 This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XE-Family Reference Manual Rev. 1.25
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