S912XEG384J3VA Datasheet, PDF (629/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 16-23. CANIDAR4–CANIDAR7 Register Field Descriptions
Field
7-0
AC[7:0]
Description
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
16.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Module Base + 0x0014 to Module Base + 0x0017
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
Access: User read/write⁽¹⁾
1
0
AM1
AM0
0
0
Figure 16-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 16-24. CANIDMR0–CANIDMR3 Register Field Descriptions
Field
Description
7-0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Module Base + 0x001C to Module Base + 0x001F
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
Access: User read/write⁽¹⁾
1
0
AM1
AM0
0
0
Figure 16-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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