S912XEG384J3VA Datasheet, PDF (457/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

TST
Test Register
Chapter 10 XGATE (S12XGATEV3)
TST
Operation
RS – 0 ⇒ NONE (translates to SUB R0, RS, R0)
Subtracts zero from the content of register RS using binary subtraction and discards the result.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & result[15]
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & result[15]
Code and CPU Cycles
Source Form
TST RS
Address
Mode
TRI
Machine Code
0 0 0 1 1 0 0 0 RS1
Cycles
00000
P
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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