S912XEG384J3VA Datasheet, PDF(576/1324 Page) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

S912XEG384J3VA Datasheet, PDF (576/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

◁

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)

At the same time the pulse accumulator is cleared.

14.4.1.4 Modulus Down-Counter

The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used

to latch the values of the IC registers and the pulse accumulators to their holding registers.

The action of latching can be programmed to be periodic or only once.

14.4.1.5 Precision Timer

By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this

case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter

and enhance delay counter settings compared to the settings in the present ECT timer.

14.4.1.6 Flag Clearing Mechanisms

The ï¬ags in the ECT can be cleared one of two ways:

1. Normal ï¬ag clearing mechanism (TFFCA = 0)

Any of the ECT ï¬ags can be cleared by writing a one to the ï¬ag.

2. Fast ï¬ag clearing mechanism (TFFCA = 1)

With the timer fast ï¬ag clear all (TFFCA) enabled, the ECT ï¬ags can only be cleared by accessing

the various registers associated with the ECT modes of operation as described below. The ï¬ags

cannot be cleared via the normal ï¬ag clearing mechanism. This fast ï¬ag clearing mechanism has

the advantage of eliminating the software overhead required by a separate clear sequence. Extra

care must be taken to avoid accidental ï¬ag clearing due to unintended accesses.

â Input capture

A read from an input capture channel register causes the corresponding channel ï¬ag, CxF, to

be cleared in the TFLG1 register.

â Output compare

A write to the output compare channel register causes the corresponding channel flag, CxF, to

be cleared in the TFLG1 register.

â Timer counter

Any access to the TCNT register clears the TOF flag in the TFLG2 register.

â Pulse accumulator A

Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the

PAFLG register.

â Pulse accumulator B

Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

â Modulus down counter

Any access to the MCCNT register clears the MCZF flag in the MCFLG register.

MC9S12XE-Family Reference Manual Rev. 1.25

576

Freescale Semiconductor

▷