S912XEG384J3VA Datasheet, PDF (75/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 1 Device Overview MC9S12XE-Family
1.3 System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-9 shows the clock connections from the CRG to all modules.
Consult the CRG specification for details on clock generation.
SCI0 . . SCI 7
CAN0 . . CAN4
SPI0 . . SPI2
IIC0 & IIC1
ATD0 & ATD1
Bus Clock
EXTAL
XTAL
CRG
Oscillator Clock
Core Clock
PIT
ECT
PIM
PWM
RAM
S12X
XGATE
FLASH &
TIM
EEE
Figure 1-9. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-9, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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