S912XEG384J3VA Datasheet, PDF (314/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.4
TRANGE
00
01
10
11
Table 8-12. TRANGE Trace Range Encoding
Tracing Range
Trace from all addresses (No filter)
Trace only in address range from $00000 to Comparator D
Trace only in address range from Comparator C to $7FFFFF
Trace only in range from Comparator C to Comparator D
Table 8-13. TRCMOD Trace Mode Bit Encoding
TRCMOD
00
01
10
11
Description
Normal
Loop1
Detail
Pure PC
TALIGN
00
01
10
11
Table 8-14. TALIGN Trace Alignment Encoding
Description
Trigger at end of stored data
Trigger before storing data
Trace buffer entries before and after trigger
Reserved
Debug Control Register2 (DBGC2)
Address: 0x0023
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
CDCM
0
0
Figure 8-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
1
0
ABCM
0
0
Table 8-15. DBGC2 Field Descriptions
Field
Description
3–2
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
CDCM[1:0] described in Table 8-16.
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 8-17.
MC9S12XE-Family Reference Manual Rev. 1.25
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