S912XEG384J3VA Datasheet, PDF (1215/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Appendix A Electrical Characteristics
Table A-10. Module Configurations for Typical Run Supply Current V_DD35=5V
Peripheral
Configuration
S12XCPU
XGATE
MSCAN
SPI
SCI
IIC
PWM
ECT
ATD
PIT
RTI
Overhead
420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
Configured to loop-back mode using a bit rate of 500kbit/s
Configured to master mode, continuously transmit data (0x55 or 0xAA) at 2Mbit/s
Configured into loop mode, continuously transmit data (0x55) at speed of 19200 baud
Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
Configured to toggle its pins at the rate of 1kHz
The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
PIT is enabled, Micro-timer register 0 and 1 loaded with $0F and timer registers 0 to 3 are loaded
with $03/07/0F/1F.
Enabled with RTI Control Register (RTICTL) set to $59
VREG supplying 1.8V from a 5V input voltage, core clock tree active, PLL on
Table A-11. Module Configurations for Maximum Run Supply Current V_DD35=5.5V
Peripheral
Configuration
S12XCPU
XGATE
MSCAN
SPI
420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
Configured to loop-back mode using a bit rate of 1Mbit/s
Configured to master mode, continuously transmit data (0x55 or 0xAA) at 4Mbit/s
SCI
Configured into loop mode, continuously transmit data (0x55) at speed of 57600 baud
IIC
Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
PWM
ECT
ATD
Overhead
Configured to toggle its pins at the rate of 40kHz
The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
VREG supplying 1.8V from a 5V input voltage, PLL on
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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