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S912XEG384J3VA Datasheet, PDF (574/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see Section 14.4.1.1, “IC Channels”).
This will prevent the captured value from being overwritten until it is read or latched in the holding
register.
2. IC Queue Mode (LATQ = 0)
The main timer value is memorized in the IC register by a valid input pin transition (see Figure 14-
69 and Figure 14-70).
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the value of the IC register will be transferred to its holding register and the IC register
memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see Section 14.4.1.1, “IC Channels”).
if the TFMOD bit of the ICSYS register is set,the timer flags C3F--C0F in TFLG register are set
only when a latch on the corresponding holding register occurs,after C3F--C0F are set,user should
clear flag C3F--C0F,then read TCx and TCxH to make TCx and TCxH be empty.
In queue mode, reads of the holding register will latch the corresponding pulse accumulator value
to its holding register.
14.4.1.1.3 Delayed IC Channels
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is
explained in the diagram and notes below.
BUS CLOCK
DLY_CNT
0
12
3
253 254 255 256
INPUT ON
CH0–3
INPUT ON
CH0–3
INPUT ON
CH0–3
255 Cycles
255.5 Cycles
255.5 Cycles
Rejected
Rejected
Accepted
INPUT ON
CH0–3
256 Cycles
Accepted
Figure 14-74. Channel Input Validity with Delay Counter Feature
In Figure 14-74 a delay counter value of 256 bus cycles is considered.
1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.
2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
accepted, depending on their relative alignment with the sample points.
MC9S12XE-Family Reference Manual Rev. 1.25
574
Freescale Semiconductor