S912XEG384J3VA Datasheet, PDF (549/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x001F
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 14-35. Timer Input Capture/Output Compare Register 7 Low (TC7)
Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
14.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Module Base + 0x0020
7
R
0
W
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-36. 16-Bit Pulse Accumulator Control Register (PACTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-19. PACTL Field Descriptions
Field
6
PAEN
5
PAMOD
Description
Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).
0 Event counter mode
1 Gated time accumulation mode
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
549