S912XEG384J3VA Datasheet, PDF(81/1324 Page) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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S912XEG384J3VA Datasheet, PDF (81/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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Chapter 1 Device Overview MC9S12XE-Family

Table 1-14. Interrupt Vector Locations (Sheet 1 of 4)

Vector Address(1)

Vector base + $F8

Vector base+ $F6

Vector base+ $F4

Vector base+ $F2

Vector base+ $F0

XGATE

Channel

ID(2)

â

â

â

â

$78

Vector base+ $EE

$77

Vector base + $EC

$76

Vector base+ $EA

$75

Vector base+ $E8

$74

Vector base+ $E6

$73

Vector base+ $E4

$72

Vector base + $E2

$71

Vector base+ $E0

$70

Vector base+ $DE

$6F

Vector base+ $DC

$6E

Vector base + $DA

$6D

Vector base + $D8

$6C

Vector base+ $D6

$6B

Vector base + $D4

$6A

Vector base + $D2

$69

Vector base + $D0

$68

Vector base + $CE

$67

Vector base + $CC

$66

Vector base + $CA

$65

Vector base + $C8

$64

Vector base + $C6

$63

Vector base + $C4

$62

Vector base + $C2

$61

Vector base + $C0

$60

Interrupt Source

CCR

Mask

Local Enable

STOP WAIT

Wake up Wake up

Unimplemented instruction trap

SWI

XIRQ

IRQ

Real time interrupt

None

None

X Bit

I bit

I bit

None

None

None

IRQCR (IRQEN)

CRGINT (RTIE)

Enhanced capture timer channel 0

Enhanced capture timer channel 1

Enhanced capture timer channel 2

Enhanced capture timer channel 3

Enhanced capture timer channel 4

Enhanced capture timer channel 5

Enhanced capture timer channel 6

Enhanced capture timer channel 7

Enhanced capture timer overï¬ow

Pulse accumulator A overï¬ow

Pulse accumulator input edge

SPI0

SCI0

SCI1

ATD0

ATD1

Port J

Port H

Modulus down counter underï¬ow

Pulse accumulator B overï¬ow

CRG PLL lock

I bit

TIE (C0I)

I bit

TIE (C1I)

I bit

TIE (C2I)

I bit

TIE (C3I)

I bit

TIE (C4I)

I bit

TIE (C5I)

I bit

TIE (C6I)

I bit

TIE (C7I)

I bit

TSRC2 (TOF)

I bit

PACTL (PAOVI)

I bit

PACTL (PAI)

I bit

SPI0CR1

(SPIE, SPTIE)

I bit

SCI0CR2

(TIE, TCIE, RIE, ILIE)

I bit

SCI1CR2

(TIE, TCIE, RIE, ILIE)

I bit ATD0CTL2 (ASCIE)

I bit ATD1CTL2 (ASCIE)

I bit PIEJ (PIEJ7-PIEJ0)

I bit PIEH (PIEH7-PIEH0)

I bit

MCCTL(MCZI)

I bit

PBCTL(PBOVI)

I bit CRGINT(LOCKIE)

CRG self-clock mode

I bit CRGINT (SCMIE)

SCI6

IIC0 bus

I bit

SCI6CR2

(TIE, TCIE, RIE, ILIE)

I bit

IBCR0 (IBIE)

â

â

â

â

Yes

Yes

Yes

Yes

Refer to CRG

interrupt section

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Refer to CRG

interrupt section

Refer to CRG

interrupt section

Yes

Yes

No

Yes

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor

81

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