S912XEG384J3VA Datasheet, PDF (688/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the
connected 16-bit modulus down-counters count one cycle.
Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the
PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF)
register is set, as shown in Figure 18-20. The time-out period is a function of the timer load (PITLD) and
micro timer load (PITMTLD) registers and the bus clock f_BUS:
time-out period = (PITMTLD + 1) * (PITLD + 1) / f_BUS.
For example, for a 40 MHz bus clock, the maximum time-out period equals:
256 * 65536 * 25 ns = 419.43 ms.
The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer
down-counter values cannot be read.
The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro
timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers
can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT
forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the
same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant
bits set, as shown in Figure 18-20.
Bus Clock
8-Bit Micro _{0 2 1 0 2 1 0 2 1 0 2 1 2 1 0 2 1 0 2 1 0 2}
Timer Counter
PITCNT Register ⁰⁰
0001
0000
0001 0000
0001
0000
0001
8-Bit Force Load
16-Bit Force Load
PTF Flag¹
PITTRIG
Time-Out Period
Note 1. The PTF flag clearing depends on the software
Time-Out Period
After Restart
Figure 18-20. PIT Trigger and Flag Signal Timing
MC9S12XE-Family Reference Manual Rev. 1.25
688
Freescale Semiconductor