S912XEG384J3VA Datasheet, PDF (157/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-68. DDR1AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 data direction—
DDR1AD0 This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR1AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.73 Port AD0 Reduced Drive Register 0 (RDR0AD0)
Address 0x0274
Access: User read/write⁽¹⁾
7
R
RDR0AD07
W
6
RDR0AD06
5
RDR0AD05
4
RDR0AD04
3
RDR0AD03
2
RDR0AD02
1
RDR0AD01
0
RDR0AD00
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-71. Port AD0 Reduced Drive Register 0 (RDR0AD0)
Table 2-69. RDR0AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 reduced drive—Select reduced drive for Port AD0 outputs
RDR0AD0 This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduced independent
of the function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
157