S912XEG384J3VA Datasheet, PDF (156/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.71 Port AD0 Data Direction Register 0 (DDR0AD0)
Address 0x0272
Access: User read/write⁽¹⁾
7
R
DDR0AD07
W
6
DDR0AD06
5
DDR0AD05
4
DDR0AD04
3
DDR0AD03
2
DDR0AD02
1
DDR0AD01
0
DDR0AD00
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
Table 2-67. DDR0AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 data direction—
DDR0AD0 This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR0AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.72 Port AD0 Data Direction Register 1 (DDR1AD0)
Address 0x0273
Access: User read/write⁽¹⁾
7
R
DDR1AD07
W
6
DDR1AD06
5
DDR1AD05
4
DDR1AD04
3
DDR1AD03
2
DDR1AD02
1
DDR1AD01
0
DDR1AD00
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)
MC9S12XE-Family Reference Manual Rev. 1.25
156
Freescale Semiconductor