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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Table 13-16. Analog Input Channel Select Coding
SC
CD
CC
CB
CA
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
X
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
X
X
X
Analog Input
Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Reserved
Reserved
Reserved
V_RH
V_RL
(V_RH+V_RL) / 2
Reserved
Reserved
13.3.2.7 ATD Status Register 0 (ATDSTAT0)
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Module Base + 0x0006
7
R
SCF
W
6
5
4
3
2
1
0
0
CC3
CC2
CC1
CC0
ETORF
FIFOR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-9. ATD Status Register 0 (ATDSTAT0)
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MC9S12XE-Family Reference Manual Rev. 1.25
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