S912XEG384J3VA Datasheet, PDF (185/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.4.4 Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-109) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-108 and
Table 2-104).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t_pign
t_pval
Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Table 2-104. Pulse Detection Criteria
Mode
Pulse
STOP
STOP⁽¹⁾
Unit
Ignored
t_pulse ≤ 3 bus clocks
t_pulse ≤ t_pign
Uncertain
3 < t_pulse < 4 bus clocks
t_pign < t_pulse < t_pval
Valid
t_pulse ≥ 4 bus clocks
t_pulse ≥ t_pval
1. These values include the spread of the oscillator frequency over temper-
ature, voltage and process.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
185