S912XEG384J3VA Datasheet, PDF (583/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
IBC5-3
(bin)
000
001
010
011
100
101
110
111
Table 15-5. Prescale Divider Encoding
scl2start
(clocks)
2
2
2
6
14
30
62
126
scl2stop
(clocks)
7
7
9
9
17
33
65
129
scl2tap
(clocks)
4
4
6
6
14
30
62
126
tap2tap
(clocks)
1
2
4
8
16
32
64
128
Table 15-6. Multiplier Factor
IBC7-6
00
01
10
11
MUL
01
02
04
RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 15-4, all subsequent tap points are separated by 2^IBC5-3 as shown in the
tap2tap column in Table 15-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 15-6.
SCL Divider
SCL
SDA
SDA Hold
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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