S912XEG384J3VA Datasheet, PDF (1243/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Appendix A Electrical Characteristics
In Figure A-8 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS1
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
1
2
4
4
5
6
MSB IN2
9
MOSI
(Output)
Port Data
Master MSB OUT2
12
12
Bit MSB-1. . . 1
11
Bit MSB-1. . . 1
13
3
13
LSB IN
Master LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure A-8. SPI Master Timing (CPHA = 1)
Port Data
Freescale Semiconductor
MC9S12XE-Family Reference Manual Rev. 1.25
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