S912XEG384J3VA Datasheet, PDF (261/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 6
Interrupt (S12XINTV2)
Table 6-1. Revision History
Revision
Number
V02.00
Revision Date
01 Jul 2005
V02.04
V02.05
V02.07
11 Jan 2007
20 Mar 2007
13 Dec 2011
Sections
Affected
6.1.2/6-262
6.3.2.2/6-267
6.3.2.4/6-268
6.4.6/6-274
6.5.3.1/6-276
Description of Changes
Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
- Added Notes for devices without XGATE module.
- Fixed priority definition for software exceptions.
- Re-worded for difference of Wake-up feature between STOP and WAIT
modes.
6.1 Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
• I bit and X bit maskable interrupt requests
• One non-maskable unimplemented op-code trap
• One non-maskable software interrupt (SWI) or background debug mode request
• One non-maskable system call interrupt (SYS)
• Three non-maskable access violation interrupts
• One spurious interrupt vector request
• Three system reset vector requests
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
NOTE
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported. It is superseded by the 7-level interrupt request
priority scheme.
MC9S12XE-Family Reference Manual Rev. 1.25
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