S912XEG384J3VA Datasheet, PDF (151/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-59. DDRJ Register Field Descriptions
Field
7
DDRJ
6
DDRJ
5
DDRJ
4
DDRJ
3
DDRJ
2
DDRJ
Description
Port J data direction—
This register controls the data direction of pin 7.
The enabled CAN4 or routed CAN0 forces the I/O state to be an output. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 6.
The enabled CAN4 or routed CAN0 forces the I/O state to be an input. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 5.
The enabled CS2 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 4.
The enabled CS0 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 3.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 2.
The enabled CS1 signal forces the I/O state to be an output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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