S912XEG384J3VA Datasheet, PDF (2/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

To provide the most up-to-date information, the document revision on the World Wide Web is the most
current. A printed copy may be an earlier revision. To verif, refer to:
freescale.com
This document contains information for the complete S12XE-Family and thus includes a set of separate
FTM module sections to cover the whole family. A full list of family members and options is included in
the appendices.
This document contains information for all constituent modules, with the exception of the S12X CPU. For
S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual.
Revision History. Refer to module section revision history tables for more information.
Date
Sep, 2008
Dec, 2008
Aug, 2009
Apr, 2010
May, 2010
Sep, 2010
Aug, 2012
Feb, 2013
Revision
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
Description
Updated NVM timing parameter section for brownout case
Specified time delay from RESET to start of CPU code execution
Added NVM patch Part IDs
Enhanced ECT GPIO / timer function transitioning description
Updated 208MAPBGA thermal parameters
Revised TIM flag clearing procedure
Corrected CRG register address
Added maskset identifier suffix for ATMC fab
Fixed typos
Added 208MAPBGA disclaimer
Added VREAPI to PT5. Added LVR Note to electricals.
Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history)
FTM section (see FTM revision history)
PIM section (see PIM revision history)
ECT and TIM sections (see ECT, TIM revision history tables)
BDM Alternate clock source defined in device overview
Added S12XEG256 option. Updated MSCAN section
Added bandgap voltage to electricals
Added new maskset and Part ID numbers
Minor updates to MSCAN,SCI and S12XINT sections
Removed BGA disclaimer
Updated MSCAN section
Formatting updates and minor corrections in PWM, CRG, BDM, DBG sections
Updated Ordering Information