S912XEG384J3VA Datasheet, PDF (580/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
• General Call Address detection
• Compliant to ten-bit address
15.1.2 Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait
and stop modes.
15.1.3 Block Diagram
The block diagram of the IIC module is shown in Figure 15-1.
IIC
Registers
Interrupt
bus_clock
Clock
Control
Start
Stop
Arbitration
Control
In/Out
Data
Shift
Register
SCL
SDA
Address
Compare
Figure 15-1. IIC Block Diagram
15.2 External Signal Description
The IICV3 module has two external pins.
15.2.1 IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
15.2.2 IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
MC9S12XE-Family Reference Manual Rev. 1.25
580
Freescale Semiconductor